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| 1 of 21 111999 features integrated nv sram, real time clock, crystal, power-fail control circuit and lithium energy source clock registers are accessed identically to the static ram; these registers are resident in the 16 top ram locations century byte register; i.e., y2k complaint totally nonvolatile with over 10 years of operation in the absence of power precision power-on reset programmable watchdog timer and rtc alarm bcd coded year, month, date, day, hours, minutes, and seconds with automatic leap year compensation valid up to the year 2100 battery voltage level indicator flag power-fail write protection allows for 10% v cc power supply tolerance lithium energy source is electrically disconnected to retain freshness until power is applied for the first time pin assignment ds1554 256k nv y2kc timekeeping ram preliminary www.dalsemi.com 1 irq/ft 2 3 nc nc rst v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 nc a 14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 34 nc x1 gnd v bat x2 34-pin powercap module board (uses ds9034pcx powercap) rst 13 1 2 3 4 5 6 7 8 9 10 11 12 14 31 a14 a7 a5 a4 a3 a2 a1 a0 dq1 dq0 v cc nc irq/ft we a 13 a 8 a 9 a 11 oe a 10 ce dq7 dq5 dq6 32 30 29 28 27 26 25 24 23 22 21 19 20 a16 a12 a6 dq2 gnd 15 16 18 17 dq4 dq3 32-pin encapsulated package
ds1554 2 of 21 ordering information ds1554p-xxx (5-volt) -70 70 ns access -100 100 ns access blank 32-pin dip module p 34-pin powercap module board* *ds1554wp-xxx (3.3 volt) -120 120 ns access -150 150 ns access blank 32-pin dip module p 34-pin powercap module board* *ds9034pcx (powercap) required: must be ordered seperately pin description a0-a14 - address input dq0-dq7 - data input/outputs irq \ft - interrupt, frequency test output (open drain) rst - power-on reset output (open drain) ce - chip enable oe - output enable we - write enable v cc - power supply input gnd - ground nc - no connection x1, x2 - crystal connection v bat - battery connection description the ds1554 is a full function, year 2000-compliant (y2kc), real-time clock/calendar (rtc) with a rtc alarm, watchdog timer, power-on reset, battery monitor, and 32k x 8 non-volatile static ram. user access to all registers within the ds1554 is accomplished with a bytewide interface as shown in figure 1. the rtc registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour bcd format. corrections for day of month and leap year are made automatically. the rtc registers are double-buffered into an internal and external set. the user has direct access to the external set. clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. assuming the internal oscillator is turned on, the internal set of registers are continuously updated; this occurs regardless of external registers settings to guarantee that accurate rtc information is always maintained. ds1554 3 of 21 the ds1554 has interrupt ( irq /ft) and reset ( rst ) outputs which can be used to control cpu activity. the irq /ft interrupt output can be used to generate an external interrupt when the rtc register values match user programmed alarm values. the interrupt is always available while the device is powered from the system supply and can be programmed to occur when in the battery backed state to serve as a system wake-up. either the irq /ft or rst outputs can also be used as a cpu watchdog timer, cpu activity is monitored and an interrupt or reset output will be activated if the correct activity is not detected within programmed limits. the ds1554 power-on reset can be used to detect a system power down or failure and hold the cpu in a safe reset state until normal power returns and stabilizes; the rst output is used for this function. the ds1554 also contains its own power-fail circuitry which automatically deselects the device when the v cc supply enters an out of tolerance condition. this feature provides a high degree of data security during unpredictable system operation brought on by low v cc levels. packages the ds1554 is available in two packages (32-pin dip and 34-pin powercap module). the 32-pin dip style module integrates the crystal, lithium energy source, and silicon all in one package. the 34-pin powercap module board is designed with contacts for connection to a separate powercap (ds9034pcx) that contains the crystal and battery. this design allows the powercap to be mounted on top of the ds1554p after the completion of the surface mount process. mounting the powercap after the surface mount process prevents damage to the crystal and battery due to the high temperatures required for solder reflow. the powercap is keyed to prevent reverse insertion. the powercap module board and powercap are ordered separately and shipped in separate containers. the part number for the powercap is ds9034pcx. ds1554 block diagram figure 1 ds1554 4 of 21 ds1554 operating modes table 1 v cc ce oe we dq0-dq7 mode power v ih x x high-z deselect standby v il xv il d in write active v il v il v ih d out read active v cc > v pf v il v ih v ih high-z read active v so < v cc ds1554 6 of 21 ds1554 register map table 2 data address b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 function/range 7fffh 10 year year year 00-99 7ffeh x x x 10 m month month 01-12 7ffdh x x 10 date date date 01-31 7ffch x ft x x x day day 01-07 7ffbh x x 10 hour hour hour 00-23 7ffah x 10 minutes minutes minutes 00-59 7ff9h osc 10 seconds seconds seconds 00-59 7ff8h w r 10 century century control 00-39 7ff7h wds bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 7ff6h ae y abe y y y y y interrupts 7ff5h am4 y 10 date date alarm date 01-31 7ff4h am3 y 10 hours hours alarm hours 00-23 7ff3h am2 10 minutes minutes alarm minutes 00-59 7ff2h am1 10 seconds seconds alarm seconds 00-59 7ff1h y y y y y y y y unused 7ff0h wf af 0 blf 0 0 0 0 flags x = unused, read/writable under write and read ae = alarm flag enable bit control y = unused, read/writable without write and read ft = frequency test bit bit control osc = oscillator start/stop bit abe = alarm in battery back-up mode enable w = write bit am1-am4 = alarm mask bits r = read bit wf = watchdog flag wds = watchdog steering bit af = alarm flag bmb0-bmb4 = watchdog multiplier bits 0 = 0 and are read only rb0-rb1 = watchdog resolution bits blf = battery low flag clock oscillator control the clock oscillator may be stopped at any time. to increase the shelf life of the backup lithium battery source, the oscillator can be turned off to minimize current drain from the battery. the osc bit is the msb of the seconds register (b7 of 7ff9h). setting it to a 1 stops the oscillator, setting to a 0 starts the oscillator. the ds1554 is shipped from dallas semiconductor with the clock oscillator turned off, osc bit set to a 1. reading the clock when reading the rtc data, it is recommended to halt updates to the external set of double-buffered rtc registers. this puts the external registers into a static state allowing data to be read without register values changing during the read process. normal updates to the internal registers continue while in this state. external updates are halted when a 1 is written into the read bit, b6 of the control register (7ff8h). as long as a 1 remains in the control register read bit, updating is halted. after a halt is issued, the registers reflect the rtc count (day, date, and time) that was current at the moment the halt command was issued. normal updates to the external set of registers will resume within 1 second after the read bit is set to a 0. ds1554 7 of 21 setting the clock the 8th bit, b7 of the control register is the write bit. setting the write bit to a 1, like the read bit, halts updates to the ds1554 (7ff8h-7fffh) registers. after setting the write bit to a 1, rtc registers can be loaded with the desired rtc count (day, date, and time) in 24-hour bcd format. setting the write bit to a 0 then transfers the values written to the internal rtc registers and allows normal operation to resume. clock accuracy (dip module) the ds1554 is guaranteed to keep time accuracy to within 1 minute per month at 25 c. the rtc is calibrated at the factory by dallas semiconductor using nonvolatile tuning elements. the ds1554 does not require additional calibration and, in most applications, temperature deviations will have a negligible effect on accuracy. for this reason, methods of field clock calibration are not available and not necessary. attempts to calibrate the rtc that may be used with similar device types (m48t5x family) will not have any effect even though the ds1554 appears to accept calibration data. clock accuracy (powercap module) the ds1554 and ds9034pcx are each individually tested for accuracy. once mounted together, the module is guaranteed to keep time accuracy to within 1.53 minutes per month (35 ppm) at 25c. frequency test mode the ds1554 frequency test mode uses the open drain irq /ft output. with the oscillator running, the irq /ft output will toggle at 512 hz when the ft bit is a 1, the alarm flag enable bit (ae) is a 0, and the watchdog steering bit (wds) is a 1 or the watchdog register is reset (register 7ff7h = 00h). the irq /ft output and the frequency test mode can be used as a measure of the actual frequency of the 32.768 khz rtc oscillator. the irq /ft pin is an open drain output which requires a pullup resistor for proper operation. the ft bit is cleared to a 0 on power-up. using the clock alarm the alarm settings and control for the ds1554 reside within registers 7ff2h-7ff5h. register 7ff6h contains two alarm enable bits: alarm enable (ae) and alarm in backup enable (abe). the ae and abe bits must be set as described below for the irq /ft output to be activated for a matched alarm condition. the alarm can be programmed to activate on a specific day of the month or repeat every day, hour, minute, or second. it can also be programmed to go off while the ds1554 is in the battery backed state of operation to serve as a system wake-up. alarm mask bits am1-am4 control the alarm mode. table 3 shows the possible settings. configurations not listed in the table default to the once per second mode to notify the user of an incorrect alarm setting. ds1554 8 of 21 alarm mask bits table 3 am4 am3 am2 am1 alarm rate 1111once per second 1110when sec onds match 1100when minutes and sec onds match 1000when hours, minutes, and seconds match 0000when date, hours, minutes, and seconds match when the rtc register values match alarm register settings, the alarm flag bit (af) is set to a 1. if alarm flag enable (ae) is also set to a 1, the alarm condition activates the irq /ft pin. the irq /ft signal is cleared by a read or write to the flags register (address 7ff0h) as shown in figure 2 and 3. the irq /ft signal may be cleared by having the address stable for as short as 15 ns and either ce or we active, but is not guaranteed to be cleared unless t rc is fulfilled. the alarm flag is also cleared by a read or write to the flags register but the flag will not change states until the end of the read/write cycle and the irq /ft signal has been cleared. clearing irq waveforms figure 2 clearing irq waveforms figure 3 ds1554 9 of 21 the irq /ft pin can also be activated in the battery backed mode. the irq /ft will go low if an alarm occurs and both abe and ae are set. the abe and ae bits are cleared during the power-up transition, however an alarm generated during power-up will set af. therefore the af bit can be read after system power-up to determine if an alarm was generated during the power-up sequence. figure 4 illustrates alarm timing during the battery back-up mode and power-up states. back-up mode alarm waveforms figure 4 using the watchdog timer the watchdog timer can be used to detect an out-of-control processor. the user programs the watchdog timer by setting the desired amount of time-out into the 8-bit watchdog register (address 7ff7h). the five watchdog register bits bmb4-bmb0 store a binary multiplier and the two lower order bits rb1- rb0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. the watchdog time-out value is then determined by the multiplication of the 5-bit multiplier value with the 2- bit resolution value. (for example: writing 00001110 in the watchdog register = 3 x 1 second or 3 seconds.) if the processor does not reset the timer within the specified period, the watchdog flag (wf) is set and a processor interrupt is generated and stays active until either the watchdog flag (wf) is read or the watchdog register (7ff7) is read or written. the most significant bit of the watchdog register is the watchdog steering bit (wds). when set to a 0, the watchdog will activate the irq /ft output when the watchdog times out. when wds is set to a 1, the watchdog will output a negative pulse on the rst output for a duration of 40 ms to 200 ms. the watchdog register (7ff7) and the ft bit will reset to a 0 at the end of a watchdog time-out when the wds bit is set to a 1. the watchdog timer resets when the processor performs a read or write of the watchdog register. the time-out period then starts over. the watchdog timer is disabled by writing a value of 00h to the watchdog register. the watchdog function is automatically disabled upon power-up and the watchdog register is cleared. if the watchdog function is set to output to the irq /ft output and the frequency test function is activated, the watchdog function prevails and the frequency test function is denied. ds1554 10 of 21 power-on default states upon application of power to the device, the following register bits are set to a 0: wds=0, bmb0-bmb4=0, rb0-rb1=0, ae=0, abe=0. absolute maximum ratings* voltage on any pin relative to ground -5.0v to +6.0v operating temperature 0 c to 70 c storage temperature -55 c to +125 c soldering temperature 260c for 10 seconds (see note 8) * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes logic 1 voltage all inputs v cc = 5v 10% v ih 2.2 v cc +0.3v v 1 v cc = 3.3v 10% v ih 2.0 v cc +0.3v v 1 logic 0 voltage all inputs v cc = 5v 10% v il -0.3 0.8 1 v cc = 3.3v 10% v il -0.3 0.6 1 dc electrical characteristics (0 c to 70 c; v cc = 5.0v = 10%) parameter symbol min typ max units notes active supply current i cc x 75 ma 2, 3 ttl standby current ( ce =v ih ) i cc1 x 6 ma 2, 3 cmos standby current ( ce = v cc - 0.2v) i cc2 x 4 ma 2, 3 input leakage current (any input) i il -1 +1 a output leakage current (any output) i ol -1 +1 a output logic 1 voltage (i out = -1.0 ma) v oh 2.4 v 1 output logic 0 voltage (i out = 2.1 ma, dq0-7 outputs) v ol1 0.4 v 1 (i out = 10.0 ma, irq /ft and rst outputs) v ol2 0.4 v 1, 5 write protection voltage v pf 4.25 4.37 4.50 v 1 battery switch over voltage v so v bat v 1, 4 ds1554 11 of 21 dc electrical characteristics (0c to 70c; v cc = 3.3v 10%) parameter symbol min typ max units notes active supply current i cc 10 30 ma 2, 3 ttl standby current ( ce = v ih ) i cc1 0.7 3 ma 2, 3 cmos standby current ( ce = v cc - 0.2v) i cc2 0.7 2 ma 2, 3 input leakage current (any input) i il -1 +1 a output leakage current (any output) i ol -1 +1 a output logic 1 voltage (i out = -1.0 ma) v oh 2.4 v 1 output logic 0 voltage (i out =2.1 ma, dq0-7 outputs) v ol1 0.4 v 1 (i out =10.0 ma, irq /ft and rst outputs) v ol2 0.4 v 1, 5 write protection voltage v pf 2.80 2.88 2.97 v 1 battery switch over voltage v so v bat or v pf v 1, 4 read cycle timing diagram figure 5 ds1554 12 of 21 read cycle, ac characteristics (0 c to 70 c; v cc = 5.0v 10%) 70 ns access 100 ns access parameter symbol min max min max units notes read cycle time t rc 70 100 ns address access time t aa 70 100 ns ce to dq low-z t cel 55 ns ce access time t cea 70 100 ns ce data off time t cez 25 35 ns oe to dq low-z t oel 55 ns oe access time t oea 35 55 ns oe data off time t oez 25 35 ns output hold from address t oh 55 ns read cycle, ac characteristics (0 c to 70 c; v cc = 3.3v 10%) 120 ns access 150 ns access parameter symbol min max min max units notes read cycle time t rc 120 150 ns address access time t aa 120 150 ns ce to dq low-z t cel 55 ns ce access time t cea 120 150 ns ce data off time t cez 40 50 ns oe to dq low-z t oel 55 ns oe access time t oea 100 130 ns oe data off time t oez 35 35 ns output hold from address t oh 55 ns ds1554 13 of 21 write cycle, ac characteristics (0 c to 70 c; v cc = 5.0v 10%) 70 ns access 100 ns access parameter symbol min max min max units notes write cycle time t wc 70 100 ns address access time t as 00 ns we pulse width t wew 50 70 ns ce pulse width t cew 60 75 ns data setup time t ds 30 40 ns data hold time t dh1 0 0 ns 9 data hold time t dh2 x x ns 10 address hold time t ah1 5 5 ns 9 address hold time t ah2 x x ns 10 we data off time t wez 25 35 ns write recovery time t wr 55 ns write cycle, ac characteristics (0 c to 70 c; v cc = 3.3v 10%) 120 ns access 150 ns access parameter symbol min max min max units notes write cycle time t wc 120 150 ns address setup time t as 00 ns we pulse width t wew 100 130 ns ce pulse width t cew 110 140 ns data setup time t ds 80 90 ns data hold time t dh1 0 0 ns 9 data hold time t dh2 x x ns 10 address hold time t ah1 0 0 ns 9 address hold time t ah2 x x ns 10 we data off time t wez 40 50 ns write recovery time t wr 10 10 ns ds1554 14 of 21 write cycle timing, write enable controlled figure 6 write cycle timing, chip enable controlled figure 7 ds1554 15 of 21 power-up/down characteristics (0 c to 70 c; v cc = 5.0v 10%) parameter symbol min typ max units notes ce or we at v ih , before power-down t pd 0 s v cc fall time: v pf(max) to v pf(min) t f 300 s v cc fall time: v pf(min) to v so t fb 10 s v cc rise time: v pf(min) to v pf(max) t r 0 s v pf to rst high t rec 40 200 ms expected data retention time (oscillator on) t dr 10 years 6, 7 power-up/down waveform timing 5-volt device figure 8 ds1554 16 of 21 power-up/down characteristics (0 c to 70 c; v cc = 3.3v 10%) parameter symbol min typ max units notes ce or we at v ih , before power-down t pd 0 s v cc fall time: v pf(max) to v pf(min) t f 300 s v cc rise time: v pf(min) to v pf(max) t r 0 s v pf to rst high t rec 40 200 ms expected data retention time (oscillator on) t dr 10 years 6, 7 power-up/down waveform timing 3.3-volt device figure 9 capacitance (t a = 25 c) parameter symbol min typ max units notes capacitance on all input pins c in 7pf1 capacitance on irq /ft, rst , and dq pins c io 10 pf 1 ds1554 17 of 21 ac test conditions output load: 100 pf + 1ttl gate input pulse levels: 0.0 to 3.0 volts timing measurement reference levels: input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns notes: 1. voltage referenced to ground. 2. typical values are at 25 c and nominal supplies. 3. outputs are open. 4. battery switch over occurs at the lower of either the battery voltage or v pf . 5. the irq /ft and rst outputs are open drain. 6. data retention time is at 25 c. 7. each ds1554 has a built-in switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined for dip modules and powercap modules as a cumulative time in the absence of v cc starting from the time power is first applied by the user. 8. real time clock modules (dip) can be successfully processed through conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85 c. post solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. in addition, for the powercap: a. dallas semiconductor recommends that powercap module bases experience one pass through solder reflow oriented with the label side up (?live-bug?). b. hand soldering and touch-up: do not touch or apply the soldering iron to leads for more than 3 seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflow and use a solder wick to remove solder. 9. t ah1 , t dh1 are measured from we going high. 10. t ah1 , t dh1 are measured from ce going high. ds1554 18 of 21 ds1554 32-pin package pkg 32-pin dim min max a in. mm 1.670 38.42 1.690 38.93 b in. mm 0.715 18.16 0.740 18.80 c in. mm 0.335 8.51 0.365 9.27 d in. mm 0.075 1.91 0.105 0.67 e in. mm 0.015 0.38 0.030 0.76 f in. mm 0.140 3.56 0.180 4.57 g in. mm 0.090 2.29 0.110 2.79 h in. mm 0.590 14.99 0.630 16.00 j in. mm 0.010 0.25 0.018 0.45 k in. mm 0.015 0.38 0.025 0.64 ds1554 19 of 21 ds1554p note: dallas semiconductor recommends that powercap module bases experience one pass through solder reflow oriented with the label side up (?live-bug?). hand soldering and touch-up: do not touch or apply the soldering iron to leads for more than 3 seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder. pkg inches dim min nom max a 0.920 0.925 0.930 b 0.980 0.985 0.990 c - - 0.080 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.025 0.027 0.030 ds1554 20 of 21 ds1554p with ds9034pcx attached pkg inches dim min nom max a 0.920 0.925 0.930 b 0.955 0.960 0.965 c 0.240 0.245 0.250 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.020 0.025 0.030 ds1554 21 of 21 recommended powercap module land pattern inches pkg dim min nom max a - 1.050 - b - 0.826 - c - 0.050 - d - 0.030 - e - 0.112 - |
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